1. Field of the Invention
The present invention relates to a MIS (Metal Insulator Semiconductor) transistor with high withstanding voltage, and a method of manufacturing a complementary transistor having such a MIS transistor. The present invention can improve the current gain of the MIS transistor.
2. Description of the Related Art
A conventional P type channel MOS (Metal Oxide Semiconductor) transistor is shown in FIG. 18A. The transistor has a drain region consisting of a high impurity concentration (P.sup.+) region 101 and an offset region 103 having a low impurity concentration (P.sup.-). A partial concentration of an electric field at the edge of a gate electrode 302 is restrained by the offset region 103. Consequently, the breakdown voltage of a drain junction of the transistor is improved. This structure is generally called "an offset gate structure".
Next, a method of manufacturing a CMOS (complementary-MOS) device having a P type channel transistor and an N type channel transistor having this offset gate structure will be explained with reference to FIGS. 20 to 23.
In FIG. 20, an N.sup.- type well region 100, a P.sup.- type well region 200, a gate oxide film 300, and a thick field oxide film (LOCOS) 301 are formed in a silicon substrate. As shown in FIG. 19, channel stopper regions 104 and 204 may be formed in the silicon substrate as the need arises. A gate electrode 302 is then selectively formed on the gate oxide film 300. A photoresist layer is deposited and selectively photoetched so that only a drain region of the N type channel transistor is uncovered. N type dopants, such as phosphorus (P), are ion-implanted into the P.sup.- type well region 200 to form a N.sup.- type offset region 203. The photoresist layer is then stripped.
In FIG. 21, a photoresist layer is deposited and selectively photoetched so that only a drain region of the P type channel transistor is uncovered. P type dopants, such as boron (B), are ion-implanted into the N.sup.- type well region 100 to form a P.sup.- type offset region 103. The photoresist layer is then stripped. It is to be noted that the order of forming the N.sup.- type offset region 203 and the P.sup.- type offset region 103 may be reversed.
In FIG. 22, a photoresist layer is deposited and selectively photoetched to uncover the regions that will form a P.sup.+ type drain region 101 and a P.sup.+ type source region 102. P type dopants are then ion-implanted into the exposed N.sup.- type well region 100,. with the photoresist used as a mask, to form the P.sup.+ type drain region 101 and the P.sup.+ type source region 102. The photoresist layer is then stripped.
In FIG. 23, a photoresist layer is deposited and selectively photoetched to uncover the regions that will form an N.sup.+ type drain region 201 and an N.sup.+ type source region 202. N type dopants are then ion-implanted into the exposed P.sup.- type well region 200, with the photoresist used as a mask, to form the N.sup.+ type drain region 201 and the N.sup.+ type source region 202. Therefore, the photoresist layer is stripped. Heat treatment is then carried out to activate the dopants.
After each region in the silicon substrate is formed, a passivation film 303 is formed. The contact portions of the passivation film 303 are opened. An electrode line 304 is formed on the passivation film 303 and the silicon substrate. Thus, a CMOS device having an offset gate structure is manufactured.
As described above, according to the conventional offset gate structure, it is necessary to carry out four photoetching steps and four ion-implanting steps to produce a high withstanding voltage structure. Specifically, the steps are to form the N.sup.- type offset region 203, the P.sup.- type offset region 103, the P.sup.+ type drain and source regions 101, 102, and the N.sup.+ type drain and source regions 201, 202. These steps are all preformed after the gate electrode 307 is formed.
Moreover, when the conventional MOS transistor shown in FIG. 18A is operated, as shown in an equivalent circuit in FIG. 18B, the offset region 103 acts as a high resistor because the impurity concentration of the offset region 103 is lower than that of the region 101. Therefore, the current gain of the MOS transistor is reduced. Especially, when the CMOS structure shown in FIG. 19 is adopted, the current gain of the device is reduced more because the size of the P type channel MOS transistor has to be bigger than that of the N type channel MOS transistor to balance between the current of the P type channel MOS transistor and that of the N type channel MOS transistor.